In a cached system, the base addresses of the last few referenced pages is maintained in registers called the TLB that aids in faster lookup. TLB contains those page-table entries that have been most recently used. Normally, each virtual memory reference causes 2 physical memory accesses- one to fetch appropriate page-table entry, and one to fetch the desired data. Using TLB in-between, this is reduced to just one physical memory access in cases of TLB-hit.
TLB, that is, Tranlation Look Aside Buffer is hardware which is used to decrease the average access time in non-contiguous memory allocation scheme. Every time a CPU generates a logical address it has to search for the frame corresponding to a page. And now as there are many displacements within a single page, the accession to main memory for finding the frame for the same page will be multiple times which increases the access time. So the first time we found the frame corresponding to a page, we store this “page-frame” entry in the TLB, so that if we need it again we could simply get it just by looking in the TLB. The accession time of TLB, being a hardware is less than that of Main memory.